Structure of semiconductor device and manufacturing method of the same

ABSTRACT

A field effect transistor configured in a convex type Fin structure, in which diffusion layer  104  serving as source and drain regions is formed in a semiconductor layer that is sandwiched by STI regions  105  and projected upward of the isolation region, and which has a gate electrode overlapping a channel region between the source and drain regions, the field effect transistor including: side walls  110   b  on the sides of the diffusion layer serving as the source and drain regions; selective epitaxial growth silicon layer  111  on the upper surface of the diffusion layer sandwiched by the side walls; and contact plug  115  connected to the selective epitaxial growth silicon layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a structure of a semiconductor deviceand a manufacturing method thereof. More particularly, the presentinvention relates to a structure of a semiconductor device, which iscapable of improving a problem in the case where contacts are formed insource and drain regions of a convex type Fin-FET (Fin Field EffectTransistor), and relates to a manufacturing method of the semiconductordevice having such structure.

2. Description of the Related Art

Along with the advancement of miniaturization of semiconductor elements,not only the gate length (channel length) but also the diffusion layerwidth (channel width) of a transistor has been increasingly reduced.Recently, attention has been given to a Fin-FET, which uses not only theupper surface but also the side surface of the diffusion layer of thetransistor as the channel to gain the on-state current (see NationalPublication of International Patent Application No. 2006-501672 andJapanese Patent Laid-Open No. 2005-310921).

Further, when the diffusion layer width (in the shorter side direction)of the Fin-FET is reduced to about 30 nm (where Lg (gate length)>W(diffusion layer width)), the channel region can be completely depleted,so that an excellent off-state current (I_(off)) characteristic can beobtained. Further, the Fin-FET has a double gate structure and hence hasa more excellent gate control characteristic as compared with a planartype transistor. For this reason, the Fin-FET is expected as acompletely depleted transistor having excellent sub-thresholdcharacteristics.

In the above described patent documents, Fin-shaped semiconductor layersare formed on an SOI substrate, and hence there is a problem thatparasitic resistance is increased in the diffusion layer.

On the other hand, there is disclosed a technique in which the Fin isformed by etching a bulk silicon substrate without using the expensiveSOI substrate (Japanese Patent Laid-Open No. 2002-118255, JapanesePatent Laid-Open No. 2006-13521 and Japanese Patent Laid-Open No.5-218415).

Further, there has been proposed a method in which a Fin-FET is formedin such a manner that after formation of STI (Shallow Trench Isolation),an insulating film buried in the STI is dug down by using a dry or wettechnique so as to expose the side surface of the diffusion layer, andthat the gate electrode is laid on the upper and side surfaces of thediffusion layer.

However, the width of the diffusion layer is only about 30 nm, whichresults in a problem that the parasitic resistance of contacts needs tobe reduced. As one of the methods to solve the problem, there has beenconsidered a method for reducing the parasitic resistance in such amanner that an epitaxial silicon is selectively grown on the side wallof the diffusion layer to thereby make the size of the contact bottomlarger than the width of the diffusion layer.

In the case where a convex type Fin-FET is produced, there is apossibility that when the epitaxial silicon is selectively grown on thesurface of the diffusion layer side, the epitaxial silicon is made togrow on the side surface of the diffusion layer. This results in aproblem that when the space separating the diffusion layers is reduceddue to the advancement of miniaturization, a short circuit is caused inthis portion.

SUMMARY OF THE INVENTION

The invention seeks to solve one or more of the above problems, or toimprove upon those problems at least in part.

As a result of an extensive investigation of the above describedproblems, the present inventors have found, as a method for surelyreducing the parasitic resistance, a method in which before an epitaxialsilicon is selectively grown, a side wall (SW) is formed on the sidesurface of the diffusion layer so that the epitaxial silicon isselectively grown only on the upper surface of the diffusion layer.

In one embodiment, there is provided a semiconductor device thatincludes: a field effect transistor configured in a convex type Finstructure having a diffusion layer serving as source and drain regionsformed in a semiconductor layer that is sandwiched by shallow trenchisolation (STI) regions and projected upward of the isolation region;and having a gate electrode overlapping a channel region between thesource and drain regions, the semiconductor device including: side wallson the sides of the diffusion layer serving as the source and drainregions; a selective epitaxial growth silicon layer on the upper surfaceof the diffusion layer sandwiched by the side walls; and a contact plugconnected to the selective epitaxial growth silicon layer.

In the present invention, the selective epitaxial growth silicon layeris formed only on the upper surface of the diffusion layer sandwiched bythe side walls. Thus, even in the case of miniaturization, the selectiveepitaxial growth silicon layers can be prevented from being brought intocontact with each other and short-circuited with each other, and thebottom size of the contact can be made larger than the width of thediffusion layer. Thereby, it is possible to reduce the parasiticresistance in the source and drain regions.

Further, in the present invention, when phosphorus and arsenic areimplanted after cell contact holes are opened, the phosphorus andarsenic can be implanted into the surface of epitaxial growth silicon ata high concentration by using the epitaxial growth silicon, so that theparasitic resistance (contact resistance) can be reduced. Further, thedistance between the bottom of the cell contact plug and the end of thegate electrode is increased, so that a margin for the leakage ofphosphorus from the cell contact plug is increased. For this reason, itis possible to increase the impurity concentration of the phosphorusdoped amorphous silicon film in the cell contact plug, so that theparasitic resistance can be further reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a layout diagram (FIG. 1( a)) of a memory cell array of aDRAM using Fin-FETs, a partially enlarged view of the memory cell array(FIG. 1( b)), and a bird's eye view (FIG. 1( c)) from the direction F inFIG. 1( b), which shows a structure of the Fin-FET. Note that in thebird's eye view, a part of the side walls 10 and 10′ is removed forexplanation, and a contact plug, an interlayer insulating film and thelike are not shown;

FIG. 2 to FIG. 12 and FIG. 14 show cross sections of a semiconductordevice, which represent the order of forming processes of a Fin-FETportion to explain a first exemplary embodiment of a manufacturingmethod according to the present invention. In the figures, each (a)shows sectional views along the line A-A in FIG. 1( b), each (b) showssectional views along the line B-B in FIG. 1( b), each (c) showssectional views along the line C-C in FIG. 1( b), each (d) showssectional views along the line D-D in FIG. 1( b), and each (e) showssectional views along the line E-E in FIG. 1( b);

FIG. 13 shows a top view after the process shown in FIG. 12;

FIG. 15 is a sectional view of a part of processes for explaining asecond exemplary embodiment; and

FIG. 16 is a sectional view showing an example of a semiconductor deviceaccording to the present invention, which is subjected to the processesup to formation of a capacitance plate of capacitors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention relates to a semiconductor device using convextype Fin-FETs in a cell array of a dynamic random access memory(hereinafter referred to as DRAM), and relates to a manufacturing methodof the semiconductor device.

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purpose.

First Exemplary Embodiment

FIG. 2 to FIG. 14 show cross sections of a semiconductor device, whichrepresent the order of forming processes of a Fin-FET portion to explainan exemplary embodiment of a manufacturing method according to thepresent invention. A sectional view of transistors in the peripheralregion is not illustrated in the figure of the exemplary embodiment.

First, as shown in FIG. 2, pad oxide film 2 having a thickness of about9 nm and field nitride film 3 having a thickness of about 120 nm aresuccessively formed on semiconductor substrate 1. Field nitride film 3serves as a mask layer covering a diffusion layer, and is also used as astopper at the time of CMP (Chemical Mechanical Polishing) of an oxidefilm which is buried in the STI. Then, patterning is performed by usinga lithography technique and a dry etching technique, so that fieldnitride film 3 and pad oxide film 2 are removed so as to open a STIforming region. Further, Si is etched to a depth of about 200 nm by adry technique using field nitride film 3 as a mask. At this time, ataper angle of diffusion layer 4 is set to 85° or more to less than 90°.Note that the upper surface of field nitride film 3 is also etched byabout 50 nm at this time.

When the Fin-FET is used in the cell array of a DRAM, a diffusion layerwidth (in the shorter side direction of convex diffusion layer 4(semiconductor layer)) of about 30 nm or less needs to be targeted torealize miniaturization in the gate width direction and a completelydepleted device using the Fin-FET. To this end, after the abovedescribed field nitride film is patterned, the field nitride film maskbefore Si etching is slimmed down to about 60 nm or less by the dryetching or the wet etching, and then Si etching is performed. As aresult of a subsequent oxidization process, and the like, the width ofthe diffusion layer is reduced to about 30 nm or less.

After the Si etching, silicon oxide film 20 is formed in the isolationtrench by a thermal oxidation method, to remove etching damage and toprotect diffusion layer 4 from the plasma of the HDP-CVD (High DensityPlasma Chemical Vapor Deposition) method as will be described below.Then, silicon oxide film 5 a is formed by the HDP-CVD method.Thereafter, silicon oxide film 5 a is polished and removed by the CMPmethod by using silicon nitride film 3 as a stopper (FIG. 3), so as tobe used as the isolation region. After the CMP, the oxide film is wetetched for adjusting the height of the STI oxide film. Then, siliconnitride film 3 is removed by wet etching. Thereby, isolation region(STI) 5 is formed (FIG. 4).

Next, impurities are implanted to form wells and channels of transistorsin the cell region and the peripheral region, and are heat treated so asto be activated (not shown). The Fin-FET has an excellent gate controlcharacteristic as compared with a planar type transistor. Thus, in theFin-FET, the channel doping for threshold adjustment is not performed,or even when the channel doping is performed, acceptor impurities areimplanted at a low concentration so that the impurity concentration inthe channel region is prevented from exceeding about 1.0×10¹⁸ cm⁻³.

Subsequently, in the above described structure, the applied resist (notshown) is opened only in the inside of the cell array by using thelithography technique, and the STI oxide film of isolation region 5 isetched to a depth of about 100 nm by the wet or dry etching technique.Thereafter, the resist is removed by ashing (FIG. 5). At this time, inthe etched region, pad oxide film 2 and silicon oxide film 20 are alsoremoved, so that the surface of diffusion layer 4 is exposed.

In the exemplary embodiment, the silicon oxide film is buried inisolation region (STI) 5. However, further miniaturization of the deviceprevents the silicon oxide film from being buried in isolation region(STI) 5 sufficiently. For this reason, an SOG (Spin-On-Glass) monolayer,or a laminated structure of the SOG and a silicon oxide film may also beused in preparation for the further miniaturization. When the SOG isreformed, a high temperature heat treatment is applied. Thus, a siliconnitride film or a silicon oxynitride film is used as a liner film. Forthis reason, in the case where the liner structure is used, when theinsulating film buried in the STI is removed, the silicon oxide film isfirst etched to about 100 nm. Thereafter, a process of removing theliner film is added, and further, silicon oxide film 20 is removed.

Next, thermal oxidation is performed to form gate insulating film 6 inabout 6 to 7 nm thick. Thereafter, polysilicon 7 used as gate electrode9 is formed in about 200 nm thick. Polysilicon 7 may contain a largeamount of phosphorus or a large amount of boron. The impurity ofpolysilicon 7 may be introduced by implantation after a non-dopedpolysilicon film is once formed, or the impurity may be introduced atthe time of film formation. (When the polysilicon containing a largeamount of boron is used as the gate electrode, it is preferred to addnitrogen by nitriding gate insulating film 6.) After polysilicon 7 isformed, polysilicon 7 is planarized to about 70 nm from the uppersurface of diffusion layer 4 by using the CMP technique. Thereafter,boron is implanted to form the channel region. The implantationcondition is set to about 65 keV/5.0E¹² cm⁻³. Then, silicon nitride film8 to be used as a hard mask is formed in about 70 nm (FIG. 6). At thistime, polysilicon 7 is used as gate electrode 9. However, there may alsobe used a multilayer gate electrode structure such as a polycidestructure having a silicide layer, such as WSi, on the polysilicon, or apoly metal structure having a metal, such as W, on the polysilicon.Thereafter, gate electrode 9 is patterned by using the lithographytechnique and the dry etching technique (FIG. 7).

Even when the width of STI and the thickness of polysilicon 7 arereduced due to the advancement of miniaturization, the STI oxide filmregion formed by etching based on the wet technique or the dry techniquecan be filled with oxide, and recessions and projections on the uppersurface of the silicon are reduced. Thereby, even when the CMP forplanarizing is not performed, it is possible to produce the polycidestructure and poly metal structure.

After patterning, the side surface portion of polysilicon of gateelectrode 9 and the substrate are selectively oxidized to several nm bythermal oxidation. Then, after the implantation of LDD (Lightly DopedDrain) regions of peripheral transistors and cell transistors isperformed, silicon nitride film 10 is formed in about 25 nm thick (FIG.8), and then etched back by the dry etching technique. At this time, thenitride film only on the upper surface of diffusion layer 4 is removed,and SiN serving as SW 10 a is left on the side surface of gate electrode9. Further, since the STI oxide film is recessed to 100 nm also in theinside of the cell, SW 10 b of silicon nitride film is also formed onthe side surface of diffusion layer 4. At this time, the STI oxide filmis also exposed (FIG. 9). In the exemplary embodiment, SW 10 b ofsilicon nitride film is illustrated in a separated state. However, asthe width of STI is reduced, the bottom portions of STI are connected toeach other, or when the width of STI is further reduced, the STI isthoroughly filled with silicon nitride. These states may also beadopted.

Thereafter, as a pretreatment to form selective epitaxial growthsilicon, the wet treatment is performed by using a solution containingHF (for example, a dilute HF solution (HF:H₂O=1:500), so that a naturaloxide film, which is formed on diffusion layer 4 exposed on the surface,is removed. Then, only on the region in which silicon is exposed, thatis, only on the upper surface of diffusion layer 4, epitaxial growthsilicon 11 is selectively grown to about 50 nm thick by the selectiveepitaxial technique. At this time, the side surface of diffusion layer 4is covered by SW 10 b of silicon nitride film, and hence epitaxialgrowth silicon 11 is not grown on the side surface of diffusion layer 4(FIG. 10). Note that epitaxial growth silicon 11 is grown in the upwarddirection and, at the same time, is also grown in the lateral direction.Thus, the width of epitaxial growth silicon 11 is slightly increased inthe width direction of diffusion layer 4, which direction is notregulated by SW 10 a of gate electrode 9. Thereby, the parasiticresistance can be reduced. As for the formed thickness of epitaxialgrowth silicon 11, it is preferred that epitaxial growth silicon 11 isformed to have a lateral width greater than the width of diffusion layer4. However, when epitaxial growth silicon 11 is formed excessivelythick, there may be a case where epitaxial growth silicon 11 overridesSW 10 b so as to be short circuited with adjacent epitaxial growthsilicon 11. Therefore, it is usually preferred that, under the conditionthat the lateral growth of the epitaxial growth silicon is suppressed asmuch as possible, epitaxial growth silicon 11 is formed to grow to suchan extent that epitaxial growth silicon 11 is not short circuited withepitaxial growth silicon of the adjacent diffusion layer. Further, asthe thickness of epitaxial growth silicon 11, a thickness of about 50 to70 nm is preferred in consideration of the condition of implantationafter cell contact holes are opened as will be described below.

Further, in the case where the epitaxial growth silicon is used, whenphosphorus and arsenic are implanted after the opening of cell contactholes as will be described below, the phosphorus and arsenic can beimplanted at a high concentration into the surface of the epitaxialgrowth silicon, so that the parasitic resistance (contact resistance)can be reduced. Further, the distance between the bottom of cell contactplug and the end of the gate electrode is increased, so that a marginfor the leakage of phosphorus from the cell contact plug is increased.For this reason, it is possible to increase the impurity concentrationof the phosphorus doped amorphous silicon film which is buried as thecell contact plug, so that the parasitic resistance can be furtherreduced.

Further, since the epitaxial growth silicon layer is provided, theposition, at which the electric field is increased due to the leakage ofphosphorus from the cell contact plug, can be separated from thevicinity of the gate electrode, which also serves to improve therefreshing characteristics.

Next, silicon nitride film 12 is formed in a thickness of about 6 nm inorder to improve a SAC (Self Align Contact) margin at the time when thecell contact holes are formed (FIG. 11). Further, although not shown, aTEOS-NSG film is formed in a thickness of about 55 nm on thesemiconductor substrate and the transistors by the CVD method.Thereafter, only the peripheral transistor region is etched back byanisotropic etching using the lithography technique and the dry etchingtechnique, so that the SW is formed. Thereafter, the TEOS-NSG film leftin the cell is further removed by the wet treatment using thelithography technique in the state where the resist is opened only inthe cell. The resist is removed by the dry etching technique after thewet treatment is finished.

Thereafter, a silicon nitride film (not shown) is formed in a thicknessof several nm. Further, a BPSG film is formed in a thickness of about600 nm to about 700 nm. Thereafter, the portion between the gate layersis filled with BPSG and the surface of the BPSG film is planarized by areflow treatment at a temperature of about 800° C. and the CMPtechnique. Then, a TEOS-NSG film is formed in a thickness of about 50 nmon the BPSG film, so that there is formed first interlayer insulatingfilm 13 made of the BPSG oxide film and the TEOS-NSG film.

Finally, as shown in FIG. 12, there are formed cell contact holes 14which are made to pass through first interlayer insulating film 13 andto reach selective epitaxial growth silicon 11. Cell contact hole 14 isetched to reach selective epitaxial growth silicon 11, and the surfaceof selective epitaxial growth silicon 11 is further over-etched by about10 nm. FIG. 13 shows a top view corresponding to FIG. 1( b) at the timewhen cell contact holes 14 have been formed.

After forming cell contact holes 14, phosphorus and arsenic areimplanted to a position shallower than the height of the Fin-FET (whichis assumed to be 100 nm in the first exemplary embodiment), so that thesource and drain regions are formed (the source electrode and the drainelectrode (in the n-type diffusion layer in this case) are not shown).The implantation condition of phosphorus is set to about 30 keV/5.0E¹²cm⁻³. The implantation condition of arsenic is set to about 25keV/1.0E¹³ cm⁻³.

After the implantation, the amorphous silicon film, in which a largeamount of phosphorus is doped, is filled in cell contact holes 14, andis deposited on first interlayer insulating film 13. Then, only thefirst silicon film on first interlayer insulating film 13 is removed byetch-back using the dry etching technique and by the CMP technique, sothat cell contact plugs 15 are formed (FIG. 14). Note that the impurityconcentration of the amorphous silicon film, in which phosphorus isdoped, is set to 1.0×10²⁰ to 4.5×10²⁰ cm⁻³. After forming cell contactplugs 15, the formation of a plasma oxide film (not shown) having athickness of about 200 nm, and heat treatment for activating theimpurities of the contact plugs are performed.

In the first exemplary embodiment, the amorphous silicon film, in whicha large amount of phosphorus is doped, is used for the cell contactplug. However, it is possible to further reduce the resistance of thecell contact plug by using a high melting point metal, such as W.However, when the high melting point metal is used, it is preferred touse a barrier metal, such as TiN, WN₂ and TaN, which prevents thediffusion of the high melting point metal.

Thereafter, contacts of the peripheral transistors, and bit lines whichare used to provide potentials to all of the transistors and portions,capacitors, wirings (Al and Cu) and the like are formed (not shown) byusing a known method. Thereby, it is possible to produce a DRAM in whichthe Fin-FET is used as the cell array transistor. For example, FIG. 16shows a cross-sectional structure after forming the capacitors. In thefigure, on the cross-sectional structure shown in FIG. 14( d) (however,respective reference numerals are changed to those on the order of 200),bit contact plug 221 connected to bit line 222, and capacitor contactplugs 223 connected to capacitors are respectively formed on the SN(Storage-Node) side. Also, cylinder type capacitors, each of which isconfigured by lower electrode polysilicon 225, capacitive insulatingfilm 226, and upper electrode metal 228, are formed in holes formed incapacitor core oxide film 224. Further, HSG (Hemi-Spherical Grainsilicon) 227 is formed on the surface of lower electrode polysilicon225, so that the capacitor area is secured.

In the exemplary embodiment shown in FIG. 16, an MIS (Metal InsulatorSemiconductor) structure, in which polysilicon with the HSG formedthereon is used as the lower electrode, is used for the concave typecapacitor structure. However, in order to cope with furtherminiaturization, there may also be used an MIM (Metal Insulator Metal)structure in which TiN, TaN, WN₂, and the like, are used for the upperelectrode and the lower electrode, and in which a single layer of one ofhigh dielectric constant films made of SiO₂, Si₃N₄, Ta₂O₅, Al₂O₃, HfO₂,ZrO₂, and the like, or a layer formed by laminating the high dielectricconstant films is used as the capacitive insulating film. There may beused a crown type capacitor structure in which the outer side of thelower electrode is also used.

In the first exemplary embodiment, diffusion layer 4 is tapered. Thus,when the thickness of the insulating film formed for SW 10 b is furtherreduced due to miniaturization, there is a possibility that the bottomside of the diffusion layer is exposed after the pretreatment (using thesolution containing HF) before epitaxial growth silicon is selectivelygrown. In the following, there will be described a second exemplaryembodiment in which a countermeasure against this problem is taken.

Second Exemplary Embodiment

Similarly to the first exemplary embodiment, Si is etched to a depth ofabout 200 nm by the dry technique using a field nitride film as a mask.At this time, a portion of diffusion layer 104 above an STI oxide film,that is, the portion having a depth of 100 nm above the STI oxide filmis vertically recessed (in the second exemplary embodiment, the STIoxide film is etched to a depth of about 100 nm in the subsequentprocess), and the portion under the vertically recessed portion isformed in a tapered shape. All of the portion having the depth of 200 nmmay be formed in a vertical shape (not shown).

Further, after the gate electrode is formed similarly to FIG. 4 to FIG.9 in the first exemplary embodiment, SiN serving as the SW is left onthe side surface of the gate electrode. Further, since the STI oxidefilm is recessed to the depth of 100 nm in the cell, the verticallyshaped portion of diffusion layer 104 is exposed on the surface of theportion, so that SW 110 b of the silicon nitride film is also formed onthe side surface. Since the recessed portion for SW 110 b at this timeis not formed in the taper shape as in the case of the first exemplaryembodiment, the thickness of the insulating film on the bottom side ofthe diffusion layer is not reduced even due to the advancement ofminiaturization. As a result, SW 110 b can be surely formed.

FIG. 15 shows a state where cell contact plugs 115 are formed byprocesses similar to the processes shown in FIG. 10 to FIG. 14 in thefirst exemplary embodiment after the above described processes. FIG. 15corresponds to FIG. 14( b). Thereafter, contacts of the peripheraltransistors, and bit lines, which are used to provide potentials to allof the transistors and portions, capacitors, wirings (Al and Cu), andthe like are formed (not shown) by using a known method. Thereby, it ispossible to produce a DRAM in which the Fin-FET is used for the cellarray transistor.

By this method, the SW can be more surely formed on the side surface ofthe diffusion layer as compared with the case of the first exemplaryembodiment, and the selective epitaxial growth silicon films on thesurface of the diffusion layer side can be prevented from being broughtinto contact with each other. Thereby, the diffusion layers can bebrought closer to each other, and hence the miniaturization can befurther advanced. Further, the second exemplary embodiment is describedby using the production flow of DRAM cell transistors, but transistorsused in logic circuits can be produced by the same method.

Note that in the exemplary embodiments, there is used polysilicon whichcontains a large amount of phosphorus in the cell contact plug. However,as a measure to reduce the resistance in the case where the size of thecell contact hole is further reduced due to the further advancement ofminiaturization, it is also possible to use a cell contact plug formedin such a manner that after phosphorus and arsenic are implantedsubsequently to the opening of the cell contact holes, a refractorymetal, such as W, is buried in the cell contact hole via a barriermetal, such as TiN and TaN. Also in this case, an excellent ohmiccontact can be formed by implanting high concentration impurities intothe epitaxial growth silicon surface.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

1. A semiconductor device which comprises a field effect transistorconfigured in a convex type Fin structure having a diffusion layerserving as source and drain regions formed in a semiconductor layer thatis sandwiched by shallow trench isolation regions and projected upwardof the isolation region; and having a gate electrode overlapping achannel region between the source and drain regions, the semiconductordevice comprising: side walls on the sides of the diffusion layerserving as the source and drain regions; a selective epitaxial growthsilicon layer on the upper surface of the diffusion layer sandwiched bythe side walls; and a contact plug connected to the selective epitaxialgrowth silicon layer.
 2. The semiconductor device according to claim 1,wherein the semiconductor layer has a width of 30 nm or less.
 3. Thesemiconductor device according to claim 1, wherein the side surface ofthe diffusion layer configured in the convex type Fin structure isformed in a taper angle of 85° or more to less than 90°.
 4. Thesemiconductor device according to claim 1, wherein the side surface ofthe diffusion layer configured in the convex Fin structure is formed ina vertical shape at least in a portion projected on the isolationregion.
 5. The semiconductor device according to claim 1, wherein afterformation of the epitaxial growth silicon layer, the source and drainregions are formed by implanting an impurity via a contact hole openedto form the contact plug.
 6. The semiconductor device according to claim1, wherein the semiconductor device is a semiconductor memory devicecomprising, as a cell transistor, the field effect transistor configuredin the convex type Fin structure.
 7. The semiconductor device accordingto claim 2, wherein the semiconductor device is a semiconductor memorydevice comprising, as a cell transistor, the field effect transistorconfigured in the convex type Fin structure.
 8. The semiconductor deviceaccording to claim 3, wherein the semiconductor device is asemiconductor memory device comprising, as a cell transistor, the fieldeffect transistor configured in the convex type Fin structure.
 9. Thesemiconductor device according to claim 4, wherein the semiconductordevice is a semiconductor memory device comprising, as a celltransistor, the field effect transistor configured in the convex typeFin structure.
 10. The semiconductor device according to claim 5,wherein the semiconductor device is a semiconductor memory devicecomprising, as a cell transistor, the field effect transistor configuredin the convex type Fin structure.
 11. A semiconductor devicemanufacturing method comprising: forming a trench serving as a shallowtrench isolation (STI) region on a semiconductor substrate; forming theSTI region by burying an insulating film in the trench; etching back apart of the insulating film of the STI region to expose a semiconductorlayer configured in a convex type Fin structure; forming a gateinsulating film on the exposed semiconductor layer; forming, on the gateinsulating film, a gate electrode overlapping a channel region betweensource and drain regions; forming side walls on the sides of the gateelectrode and on the sides of the semiconductor layer serving as thesource and drain regions, and at the same time, exposing the uppersurface of the semiconductor layer serving as the source and drainregions; forming a selective epitaxial growth silicon layer on theexposed upper surface of the exposed semiconductor layer; forming aninterlayer insulating film and a contact hole connected to thesemiconductor layer on which the selective epitaxial growth siliconlayer is formed; and forming a contact plug by burying a conductivematerial in the contact hole.
 12. The semiconductor device manufacturingmethod according to claim 11, wherein the trench forming the STI regionis formed in a taper angle of 85° or more to less than 90°.
 13. Thesemiconductor device manufacturing method according to claim 11, whereinthe trench forming the STI region is formed so that at least a portionof the semiconductor layer, which portion is projected on the isolationregion, is formed in a vertical shape.
 14. The semiconductor devicemanufacturing method according to claim 11, wherein after formation ofthe epitaxial growth silicon layer, the source and drain regions areformed as a diffusion layer by implanting an impurity via the contacthole opened to form the contact plug.
 15. The semiconductor devicemanufacturing method according to claim 12, wherein after formation ofthe epitaxial growth silicon layer, the source and drain regions areformed as a diffusion layer by implanting an impurity via the contacthole opened to form the contact plug.
 16. The semiconductor devicemanufacturing method according to claim 13, wherein after formation ofthe epitaxial growth silicon layer, the source and drain regions areformed as a diffusion layer by implanting an impurity via the contacthole opened to form the contact plug.